Hardware Accelerators for NLP applications
At CFAED TU Dresden, 2022
Developed Hardware Accelerators for Transformer Encoders and BERT models to perform various Natural Language Processing tasks with focus on resource constrained devices. Read more
At CFAED TU Dresden, 2022
Developed Hardware Accelerators for Transformer Encoders and BERT models to perform various Natural Language Processing tasks with focus on resource constrained devices. Read more
At BITS Pilani, 2022
Functional verification of Network-on-Chip systems using a feedback guided test generation approach Read more
At BITS Pilani, 2021
Parallel execution of convolution algorithm to test a RISC-V based NoC Read more
At BITS Pilani, 2021
Designed and developed a RISC-V processor in Verilog as a part of my course project in computer architecture course Read more
At BITS Pilani, 2020
Worked on Kalman Filter techniques for stability issues and state estimation of voltages to avoid voltage regulation issues in multiple Distributed Energy Resources. Read more
At BITS Pilani, 2020
Electrical and Electronics Subsystem Lead Read more
At somewhere-on-earth, 2020
Other random projects that I did during my undergrad. Read more