RISC-V Processor

Abstract: A 32-bit, 5-stage pipelined processor with Fetch, Decode, Execute, Memory, and Write-Back stages in Verilog. Implemented a forwarding unit and hazard-detection unit for resolving data, stall, and control hazards. The processor supports few arithmetic, immediate, load/store, and branch instructions from the RV-32I ISA. The code and the other details regarding the course can be found in this repository.