Verification of Network-On-Chip Systems

Abstract: On-chip interconnects like Network-on-Chip (NoC) have replaced the traditional hierarchical buses or crossbar inter-connects in the new generation System-on-Chips (SoCs) as they provide a front-end solution to the backend routing congestion problem. The NoC interconnects are highly efficient and configurable. Ensuring the functional correctness of such interconnects is challenging due to many links. Therefore, automating the NoC functional verification process is vital to help reduce the time-to- market of such complex SoC designs. In this work, we develop Feedback Guided Generation (FGG) technique to automate and accelerate the process. The FGG uses the initial coverage metrics as feedback and accelerates the functional coverage closure by developing an efficient test stimulus, ensuring lesser verification time. On Comparison with existing Constraint Random Verification (CRV) methods, the FGG shows as high as 88% improvement in time and the number of packets that need to be generated to achieve 100% functional coverage.